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authorMarc Zyngier <marc.zyngier@arm.com>2016-12-20 15:20:38 +0000
committerMarc Zyngier <marc.zyngier@arm.com>2017-08-31 15:31:38 +0100
commitf6a91da7c788ac7345305ee291d0b205d2f5a70f (patch)
tree559000b999db33baa125b9ea604757058ec62f9c /arch/arm64/include/asm/arch_gicv3.h
parentirqchip/gic-v3-its: Add VPE affinity changes (diff)
downloadlinux-dev-f6a91da7c788ac7345305ee291d0b205d2f5a70f.tar.xz
linux-dev-f6a91da7c788ac7345305ee291d0b205d2f5a70f.zip
irqchip/gic-v3-its: Add VPE interrupt masking
When masking/unmasking a doorbell interrupt, it is necessary to issue an invalidation to the corresponding redistributor. We use the DirectLPI feature by writting directly to the corresponding redistributor. Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to '')
-rw-r--r--arch/arm64/include/asm/arch_gicv3.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 0d2a53457c30..b7e3f74822da 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -116,6 +116,8 @@ static inline void gic_write_bpr1(u32 val)
#define gic_read_typer(c) readq_relaxed(c)
#define gic_write_irouter(v, c) writeq_relaxed(v, c)
+#define gic_read_lpir(c) readq_relaxed(c)
+#define gic_write_lpir(v, c) writeq_relaxed(v, c)
#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))