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authorWill Deacon <will.deacon@arm.com>2015-05-29 13:31:10 +0100
committerWill Deacon <will.deacon@arm.com>2015-07-27 15:28:53 +0100
commit0ea366f5e1b6413a6095dce60ea49ae51e468b61 (patch)
treefce4fc690edf16784d21a714415a74a8ce53eb2b /arch/arm64/include/asm/futex.h
parentarm64: atomics: tidy up common atomic{,64}_* macros (diff)
downloadlinux-dev-0ea366f5e1b6413a6095dce60ea49ae51e468b61.tar.xz
linux-dev-0ea366f5e1b6413a6095dce60ea49ae51e468b61.zip
arm64: atomics: prefetch the destination word for write prior to stxr
The cost of changing a cacheline from shared to exclusive state can be significant, especially when this is triggered by an exclusive store, since it may result in having to retry the transaction. This patch makes use of prfm to prefetch cachelines for write prior to ldxr/stxr loops when using the ll/sc atomic routines. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to '')
-rw-r--r--arch/arm64/include/asm/futex.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h
index 775e85b9d1f2..007a69fc4f40 100644
--- a/arch/arm64/include/asm/futex.h
+++ b/arch/arm64/include/asm/futex.h
@@ -30,6 +30,7 @@
asm volatile( \
ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \
CONFIG_ARM64_PAN) \
+" prfm pstl1strm, %2\n" \
"1: ldxr %w1, %2\n" \
insn "\n" \
"2: stlxr %w3, %w0, %2\n" \
@@ -120,6 +121,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
return -EFAULT;
asm volatile("// futex_atomic_cmpxchg_inatomic\n"
+" prfm pstl1strm, %2\n"
"1: ldxr %w1, %2\n"
" sub %w3, %w1, %w4\n"
" cbnz %w3, 3f\n"