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| author |   Will Deacon <will.deacon@arm.com> | 2018-08-22 21:36:31 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2018-09-11 16:49:11 +0100 |
| commit | 0795edaf3f1ff1ea58048515211280db004bbd68 (patch) | |
| tree | 5740e9da7ea7de64914d8d6370c448269574f30c /arch/arm64/include/asm/tlbflush.h | |
| parent | arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable() (diff) | |
| download | linux-dev-0795edaf3f1ff1ea58048515211280db004bbd68.tar.xz linux-dev-0795edaf3f1ff1ea58048515211280db004bbd68.zip | |
arm64: pgtable: Implement p[mu]d_valid() and check in set_p[mu]d()
Now that our walk-cache invalidation routines imply a DSB before the
invalidation, we no longer need one when we are clearing an entry during
unmap.
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions