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| author |   James Morse <james.morse@arm.com> | 2022-09-30 14:19:59 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2022-10-07 14:42:20 +0100 |
| commit | 171df58028bf4649460fb146a56a58dcb0c8f75a (patch) | |
| tree | f2d404265dbde354b2f6768c8c66e3eab4015e19 /arch/arm64/kernel/cpu_errata.c | |
| parent | arm64/sysreg: Fix typo in SCTR_EL1.SPINTMASK (diff) | |
| download | linux-dev-171df58028bf4649460fb146a56a58dcb0c8f75a.tar.xz linux-dev-171df58028bf4649460fb146a56a58dcb0c8f75a.zip | |
arm64: errata: Add Cortex-A55 to the repeat tlbi list
Cortex-A55 is affected by an erratum where in rare circumstances the
CPUs may not handle a race between a break-before-make sequence on one
CPU, and another CPU accessing the same page. This could allow a store
to a page that has been unmapped.
Work around this by adding the affected CPUs to the list that needs
TLB sequences to be done twice.
Signed-off-by: James Morse <james.morse@arm.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220930131959.3082594-1-james.morse@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 58ca4f6b25d6..89ac00084f38 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -230,6 +230,11 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), }, #endif +#ifdef CONFIG_ARM64_ERRATUM_2441007 + { + ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + }, +#endif #ifdef CONFIG_ARM64_ERRATUM_2441009 { /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */ |