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authorRobin Murphy <robin.murphy@arm.com>2017-07-25 11:55:41 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2017-08-09 11:00:43 +0100
commite1bc5d1b8e0547c258e65dd97a03560f4d69e635 (patch)
tree421aea530d18c65528ece256b0789dc3b05aa2e1 /arch/arm64/kernel
parentarm64: Expose DC CVAP to userspace (diff)
downloadlinux-dev-e1bc5d1b8e0547c258e65dd97a03560f4d69e635.tar.xz
linux-dev-e1bc5d1b8e0547c258e65dd97a03560f4d69e635.zip
arm64: Handle trapped DC CVAP
Cache clean to PoP is subject to the same access controls as to PoC, so if we are trapping userspace cache maintenance with SCTLR_EL1.UCI, we need to be prepared to handle it. To avoid getting into complicated fights with binutils about ARMv8.2 options, we'll just cheat and use the raw SYS instruction rather than the 'proper' DC alias. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel')
-rw-r--r--arch/arm64/kernel/traps.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 0f047e916cee..ccb9727d67b2 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -484,6 +484,9 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
__user_cache_maint("dc civac", address, ret);
break;
+ case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */
+ __user_cache_maint("sys 3, c7, c12, 1", address, ret);
+ break;
case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */
__user_cache_maint("dc civac", address, ret);
break;