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authorWill Deacon <will.deacon@arm.com>2015-10-06 18:46:27 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2015-10-07 11:56:25 +0100
commitc2775b2ee5caca19f661ee2ab5af92462596db71 (patch)
treeebcc6eb88426e864d8f716543e69f398f1fc1c91 /arch/arm64/mm/context.c
parentarm64: tlbflush: avoid flushing when fullmm == 1 (diff)
downloadlinux-dev-c2775b2ee5caca19f661ee2ab5af92462596db71.tar.xz
linux-dev-c2775b2ee5caca19f661ee2ab5af92462596db71.zip
arm64: switch_mm: simplify mm and CPU checks
switch_mm performs some checks to try and avoid entering the ASID allocator: (1) If we're switching to the init_mm (no user mappings), then simply set a reserved TTBR0 value with no page table (the zero page) (2) If prev == next *and* the mm_cpumask indicates that we've run on this CPU before, then we can skip the allocator. However, there is plenty of redundancy here. With the new ASID allocator, if prev == next, then we know that our ASID is valid and do not need to worry about re-allocation. Consequently, we can drop the mm_cpumask check in (2) and move the prev == next check before the init_mm check, since if prev == next == init_mm then there's nothing to do. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to '')
-rw-r--r--arch/arm64/mm/context.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index e902229b1a3d..4b9ec4484e3f 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -166,10 +166,10 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
local_flush_tlb_all();
atomic64_set(&per_cpu(active_asids, cpu), asid);
- cpumask_set_cpu(cpu, mm_cpumask(mm));
raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
switch_mm_fastpath:
+ cpumask_set_cpu(cpu, mm_cpumask(mm));
cpu_switch_mm(mm->pgd, mm);
}