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authorAshok Kumar <ashoks@broadcom.com>2015-12-17 01:38:32 -0800
committerWill Deacon <will.deacon@arm.com>2015-12-17 11:07:13 +0000
commit0a28714c53fd4f7aea709be7577dfbe0095c8c3e (patch)
tree344737ce5e2fdb5ade93d053c49efd9a05c70bfa /arch/arm64/mm/hugetlbpage.c
parentarm64: Defer dcache flush in __cpu_copy_user_page (diff)
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arm64: Use PoU cache instr for I/D coherency
In systems with three levels of cache(PoU at L1 and PoC at L3), PoC cache flush instructions flushes L2 and L3 caches which could affect performance. For cache flushes for I and D coherency, PoU should suffice. So changing all I and D coherency related cache flushes to PoU. Introduced a new __clean_dcache_area_pou API for dcache flush till PoU and provided a common macro for __flush_dcache_area and __clean_dcache_area_pou. Also, now in __sync_icache_dcache, icache invalidation for non-aliasing VIPT icache is done only for that particular page instead of the earlier __flush_icache_all. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ashok Kumar <ashoks@broadcom.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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