path: root/arch/arm64/mm/hugetlbpage.c
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authorSteve Capper <steve.capper@linaro.org>2013-05-28 13:35:51 +0100
committerSteve Capper <steve.capper@linaro.org>2013-06-14 09:52:19 +0100
commit59911ca4325dc7bd95e05c988fef3593b694e62c (patch)
treecc4a255ac8b12f57f946900f6c52e850691b2433 /arch/arm64/mm/hugetlbpage.c
parentARM64: mm: Make PAGE_NONE pages read only and no-execute. (diff)
ARM64: mm: Move PTE_PROT_NONE bit.
Under ARM64, PTEs can be broadly categorised as follows: - Present and valid: Bit #0 is set. The PTE is valid and memory access to the region may fault. - Present and invalid: Bit #0 is clear and bit #1 is set. Represents present memory with PROT_NONE protection. The PTE is an invalid entry, and the user fault handler will raise a SIGSEGV. - Not present (file or swap): Bits #0 and #1 are clear. Memory represented has been paged out. The PTE is an invalid entry, and the fault handler will try and re-populate the memory where necessary. Huge PTEs are block descriptors that have bit #1 clear. If we wish to represent PROT_NONE huge PTEs we then run into a problem as there is no way to distinguish between regular and huge PTEs if we set bit #1. To resolve this ambiguity this patch moves PTE_PROT_NONE from bit #1 to bit #2 and moves PTE_FILE from bit #2 to bit #3. The number of swap/file bits is reduced by 1 as a consequence, leaving 60 bits for file and swap entries. Signed-off-by: Steve Capper <steve.capper@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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