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authorVladimir Murzin <vladimir.murzin@arm.com>2019-02-20 11:43:05 +0000
committerWill Deacon <will.deacon@arm.com>2019-02-20 14:05:37 +0000
commit74698f6971f25d045301139413578865fc2bd8f9 (patch)
treec7746935f5718abdf8ff17f15647e0d8207d3107 /arch/arm64
parentarm64/neon: Disable -Wincompatible-pointer-types when building with Clang (diff)
downloadlinux-dev-74698f6971f25d045301139413578865fc2bd8f9.tar.xz
linux-dev-74698f6971f25d045301139413578865fc2bd8f9.zip
arm64: Relax GIC version check during early boot
Updates to the GIC architecture allow ID_AA64PFR0_EL1.GIC to have values other than 0 or 1. At the moment, Linux is quite strict in the way it handles this field at early boot stage (cpufeature is fine) and will refuse to use the system register CPU interface if it doesn't find the value 1. Fixes: 021f653791ad17e03f98aaa7fb933816ae16f161 ("irqchip: gic-v3: Initial support for GICv3") Reported-by: Chase Conklin <Chase.Conklin@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/kernel/head.S3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 15d79a8e5e5e..eecf7927dab0 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -539,8 +539,7 @@ set_hcr:
/* GICv3 system register access */
mrs x0, id_aa64pfr0_el1
ubfx x0, x0, #24, #4
- cmp x0, #1
- b.ne 3f
+ cbz x0, 3f
mrs_s x0, SYS_ICC_SRE_EL2
orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1