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| author |   Rich Wiley <rwiley@nvidia.com> | 2019-11-05 10:45:10 -0800 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2019-11-06 11:31:03 +0000 |
| commit | 918e1946c8ac2c0473eefc1dc910780178490e95 (patch) | |
| tree | 5af7dc62824e0a0734af83682179da6a1d34b471 /arch/arm64 | |
| parent | arm64: mm: Remove MAX_USER_VA_BITS definition (diff) | |
| download | linux-dev-918e1946c8ac2c0473eefc1dc910780178490e95.tar.xz linux-dev-918e1946c8ac2c0473eefc1dc910780178490e95.zip | |
arm64: kpti: Add NVIDIA's Carmel core to the KPTI whitelist
NVIDIA Carmel CPUs don't implement ID_AA64PFR0_EL1.CSV3 but
aren't susceptible to Meltdown, so add Carmel to kpti_safe_list[].
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index cabebf1a7976..b3eea965c930 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -977,6 +977,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), { /* sentinel */ } }; char const *str = "kpti command line option"; |