diff options
| author |   Michael Hennerich <michael.hennerich@analog.com> | 2008-07-14 16:51:57 +0800 |
|---|---|---|
| committer |   Bryan Wu <cooloney@kernel.org> | 2008-07-14 16:51:57 +0800 |
| commit | 68e2fc78e5055740126df8eab0d31005495756c9 (patch) | |
| tree | 0d43976ff1d3ae8535445f9bcb1687f657f33337 /arch/blackfin/mach-bf537/head.S | |
| parent | Blackfin arch: Fix bug - do not overflow the buffer given to us which tends to happen when CONFIG_L1_MAX_PIECE is increased past its default (diff) | |
| download | linux-dev-68e2fc78e5055740126df8eab0d31005495756c9.tar.xz linux-dev-68e2fc78e5055740126df8eab0d31005495756c9.zip | |
Blackfin arch: Fix bug - Kernel does not boot if re-program clocks
Don't write conflicting data to EBIU_SDBCTL after the SDRAM is
configured. This can cause data corruption, since we might change SDRAM
row and column addressing modes.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/blackfin/mach-bf537/head.S | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 48cd58a410a0..6b019eaee0b6 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -32,7 +32,7 @@ #include <asm/blackfin.h> #include <asm/trace.h> -#if CONFIG_BFIN_KERNEL_CLOCK +#ifdef CONFIG_BFIN_KERNEL_CLOCK #include <asm/mach-common/clocks.h> #include <asm/mach/mem_init.h> #endif @@ -217,7 +217,7 @@ ENTRY(__start) /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ call _bf53x_relocate_l1_mem; -#if CONFIG_BFIN_KERNEL_CLOCK +#ifdef CONFIG_BFIN_KERNEL_CLOCK call _start_dma_code; #endif @@ -350,7 +350,7 @@ ENDPROC(_real_start) __FINIT .section .l1.text -#if CONFIG_BFIN_KERNEL_CLOCK +#ifdef CONFIG_BFIN_KERNEL_CLOCK ENTRY(_start_dma_code) /* Enable PHY CLK buffer output */ @@ -430,12 +430,6 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; - p0.l = LO(EBIU_SDBCTL); - p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ - r0 = mem_SDBCTL; - w[p0] = r0.l; - ssync; - P2.H = hi(EBIU_SDGCTL); P2.L = lo(EBIU_SDGCTL); R0 = [P2]; |