diff options
| author |   Mike Frysinger <vapier.adi@gmail.com> | 2008-08-06 17:05:20 +0800 |
|---|---|---|
| committer |   Bryan Wu <cooloney@kernel.org> | 2008-08-06 17:05:20 +0800 |
| commit | 778307d372555f979cf6cef112a6d7fbff056cd9 (patch) | |
| tree | 6ab304d2f1ef333f48b56eb2913268fe9dfc9714 /arch/blackfin/mach-bf537 | |
| parent | Blackfin arch: Fix bugs - Make kgdb code apparent to app debugging. (diff) | |
| download | linux-dev-778307d372555f979cf6cef112a6d7fbff056cd9.tar.xz linux-dev-778307d372555f979cf6cef112a6d7fbff056cd9.zip | |
Blackfin arch: remove support for Anomaly 05000125 as it doesnt exist on any supported processor/silicon
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/blackfin/mach-bf537/head.S | 39 |
1 files changed, 1 insertions, 38 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 6b019eaee0b6..5bc89bbb89d0 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -105,17 +105,8 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; - - /* Anomaly 05000125 */ -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif /* Turn off the dcache */ p0.l = LO(DMEM_CONTROL); @@ -123,48 +114,20 @@ ENTRY(__start) R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; - - /* Anomaly 05000125 */ -#if ANOMALY_05000125 - CLI R2; - SSYNC; -#endif [p0] = R0; SSYNC; -#if ANOMALY_05000125 - STI R2; -#endif /* Initialise General-Purpose I/O Modules on BF537 */ - /* Rev 0.0 Anomaly 05000212 - PORTx_FER, - * PORT_MUX Registers Do Not accept "writes" correctly: - */ p0.h = hi(BFIN_PORT_MUX); p0.l = lo(BFIN_PORT_MUX); -#if ANOMALY_05000212 - R0.L = W[P0]; /* Read */ - SSYNC; -#endif R0 = (PGDE_UART | PFTE_UART)(Z); -#if ANOMALY_05000212 - W[P0] = R0.L; /* Write */ - SSYNC; -#endif W[P0] = R0.L; /* Enable both UARTS */ SSYNC; + /* Enable peripheral function of PORTF for UART0 and UART1 */ p0.h = hi(PORTF_FER); p0.l = lo(PORTF_FER); -#if ANOMALY_05000212 - R0.L = W[P0]; /* Read */ - SSYNC; -#endif R0 = 0x000F(Z); -#if ANOMALY_05000212 - W[P0] = R0.L; /* Write */ - SSYNC; -#endif - /* Enable peripheral function of PORTF for UART0 and UART1 */ W[P0] = R0.L; SSYNC; |