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| author |   Mike Frysinger <vapier.adi@gmail.com> | 2008-08-06 17:17:10 +0800 |
|---|---|---|
| committer |   Bryan Wu <cooloney@kernel.org> | 2008-08-06 17:17:10 +0800 |
| commit | 7e64acabfdb530b1b7d3db2592d75d102827baf3 (patch) | |
| tree | 9cd5d29f86a700fa474f063462bad928d292b567 /arch/blackfin/mach-bf537 | |
| parent | Blackfin arch: make sure the BSS and kernel load address are 4 byte aligned (diff) | |
| download | linux-dev-7e64acabfdb530b1b7d3db2592d75d102827baf3.tar.xz linux-dev-7e64acabfdb530b1b7d3db2592d75d102827baf3.zip | |
Blackfin arch: move async memory programming into common setup_arch() as the banks dont really need to be setup fully as early as head.S
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/blackfin/mach-bf537/head.S | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index c11f0fd82255..c062acb04836 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -184,28 +184,6 @@ ENTRY(__start) call _start_dma_code; #endif - /* Code for initializing Async memory banks */ - - p2.h = hi(EBIU_AMBCTL1); - p2.l = lo(EBIU_AMBCTL1); - r0.h = hi(AMBCTL1VAL); - r0.l = lo(AMBCTL1VAL); - [p2] = r0; - ssync; - - p2.h = hi(EBIU_AMBCTL0); - p2.l = lo(EBIU_AMBCTL0); - r0.h = hi(AMBCTL0VAL); - r0.l = lo(AMBCTL0VAL); - [p2] = r0; - ssync; - - p2.h = hi(EBIU_AMGCTL); - p2.l = lo(EBIU_AMGCTL); - r0 = AMGCTLVAL; - w[p2] = r0; - ssync; - /* This section keeps the processor in supervisor mode * during kernel boot. Switches to user mode at end of boot. * See page 3-9 of Hardware Reference manual for documentation. |