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| author |   Mike Frysinger <vapier.adi@gmail.com> | 2008-08-14 14:29:57 +0800 |
|---|---|---|
| committer |   Bryan Wu <cooloney@kernel.org> | 2008-08-14 14:29:57 +0800 |
| commit | 0e06b50dda5965e0f8a15b0be14b759ead54fd2a (patch) | |
| tree | 3b0bf1ba71ba8799e55a7670d8572615443c0ba5 /arch/blackfin/mach-common/lock.S | |
| parent | Blackfin arch: workaround SIC_IWR1 reset bug, by keeping MDMA0/1 always enabled in SIC_IWR1. (diff) | |
| download | linux-dev-0e06b50dda5965e0f8a15b0be14b759ead54fd2a.tar.xz linux-dev-0e06b50dda5965e0f8a15b0be14b759ead54fd2a.zip | |
Blackfin arch: cleanup cache lock code
- remove cheesy read_iloc() function
- move invalidate_entire_icache function to lock.S
- export proper prototypes for functions in lock.S
- only build lock.S when BFIN_ICACHE_LOCK is enabled
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/blackfin/mach-common/lock.S | 45 |
1 files changed, 31 insertions, 14 deletions
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S index 30b887e67dd6..9daf01201e9f 100644 --- a/arch/blackfin/mach-common/lock.S +++ b/arch/blackfin/mach-common/lock.S @@ -28,13 +28,10 @@ */ #include <linux/linkage.h> -#include <asm/cplb.h> #include <asm/blackfin.h> .text -#ifdef CONFIG_BFIN_ICACHE_LOCK - /* When you come here, it is assumed that * R0 - Which way to be locked */ @@ -189,18 +186,38 @@ ENTRY(_cache_lock) RTS; ENDPROC(_cache_lock) -#endif /* BFIN_ICACHE_LOCK */ - -/* Return the ILOC bits of IMEM_CONTROL +/* Invalidate the Entire Instruction cache by + * disabling IMC bit */ +ENTRY(_invalidate_entire_icache) + [--SP] = ( R7:5); -ENTRY(_read_iloc) - P1.H = HI(IMEM_CONTROL); - P1.L = LO(IMEM_CONTROL); - R1 = 0xF; - R0 = [P1]; - R0 = R0 >> 3; - R0 = R0 & R1; + P0.L = LO(IMEM_CONTROL); + P0.H = HI(IMEM_CONTROL); + R7 = [P0]; + + /* Clear the IMC bit , All valid bits in the instruction + * cache are set to the invalid state + */ + BITCLR(R7,IMC_P); + CLI R6; + SSYNC; /* SSYNC required before invalidating cache. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the instruction cache agian */ + R6 = (IMC | ENICPLB); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + ( R7:5) = [SP++]; RTS; -ENDPROC(_read_iloc) +ENDPROC(_invalidate_entire_icache) |