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| author |   Michael Hennerich <michael.hennerich@analog.com> | 2007-06-21 11:34:16 +0800 |
|---|---|---|
| committer |   Bryan Wu <bryan.wu@analog.com> | 2007-06-21 11:34:16 +0800 |
| commit | 1c5d2265a82f8d3fa0471a60ca98072b3c53c299 (patch) | |
| tree | d0644427e9d700df594fa8dbcbb1338bfd982ac2 /arch/blackfin | |
| parent | Blackfin arch: need to rename function after moving to match new internal dma API (diff) | |
| download | linux-dev-1c5d2265a82f8d3fa0471a60ca98072b3c53c299.tar.xz linux-dev-1c5d2265a82f8d3fa0471a60ca98072b3c53c299.zip | |
Blackfin arch: add missing implementations SIC_IWR crosses several registers
SIC_IWR crosses several registers
- add missing implementations
- make sure SIC_IWR is SET after boot
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/blackfin/mach-common/ints-priority-dc.c | 3 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/ints-priority-sc.c | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c index 80943bbd37c2..e6511db24032 100644 --- a/arch/blackfin/mach-common/ints-priority-dc.c +++ b/arch/blackfin/mach-common/ints-priority-dc.c @@ -371,6 +371,9 @@ int __init init_arch_irq(void) bfin_write_SICA_IMASK1(SIC_UNMASK_ALL); SSYNC(); + bfin_write_SICA_IWR0(IWR_ENABLE_ALL); + bfin_write_SICA_IWR1(IWR_ENABLE_ALL); + local_irq_disable(); init_exception_buff(); diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index cec0f841fb5a..27838da55d6c 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -472,8 +472,12 @@ int __init init_arch_irq(void) bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); + bfin_write_SIC_IWR0(IWR_ENABLE_ALL); + bfin_write_SIC_IWR1(IWR_ENABLE_ALL); + bfin_write_SIC_IWR2(IWR_ENABLE_ALL); #else bfin_write_SIC_IMASK(SIC_UNMASK_ALL); + bfin_write_SIC_IWR(IWR_ENABLE_ALL); #endif SSYNC(); |