path: root/arch/i386/kernel/apic.c
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authorFernando Luis VazquezCao <fernando@oss.ntt.co.jp>2007-05-02 19:27:17 +0200
committerAndi Kleen <andi@basil.nowhere.org>2007-05-02 19:27:17 +0200
commitf2b218dd6199983b120a96bc6531c1b81f4090d8 (patch)
treec698c752d4424e926badbfe1bda2ff5c738cacf6 /arch/i386/kernel/apic.c
parent[PATCH] i386: Enable support for fixed-range IORRs to keep RdMem & WrMem in sync (diff)
[PATCH] i386: safe_apic_wait_icr_idle - i386
apic_wait_icr_idle looks like this: static __inline__ void apic_wait_icr_idle(void) { while (apic_read(APIC_ICR) & APIC_ICR_BUSY) cpu_relax(); } The busy loop in this function would not be problematic if the corresponding status bit in the ICR were always updated, but that does not seem to be the case under certain crash scenarios. Kdump uses an IPI to stop the other CPUs in the event of a crash, but when any of the other CPUs are locked-up inside the NMI handler the CPU that sends the IPI will end up looping forever in the ICR check, effectively hard-locking the whole system. Quoting from Intel's "MultiProcessor Specification" (Version 1.4), B-3: "A local APIC unit indicates successful dispatch of an IPI by resetting the Delivery Status bit in the Interrupt Command Register (ICR). The operating system polls the delivery status bit after sending an INIT or STARTUP IPI until the command has been dispatched. A period of 20 microseconds should be sufficient for IPI dispatch to complete under normal operating conditions. If the IPI is not successfully dispatched, the operating system can abort the command. Alternatively, the operating system can retry the IPI by writing the lower 32-bit double word of the ICR. This “time-out” mechanism can be implemented through an external interrupt, if interrupts are enabled on the processor, or through execution of an instruction or time-stamp counter spin loop." Intel's documentation suggests the implementation of a time-out mechanism, which, by the way, is already being open-coded in some parts of the kernel that tinker with ICR. Create a apic_wait_icr_idle replacement that implements the time-out mechanism and that can be used to solve the aforementioned problem. AK: moved both functions out of line AK: added improved loop from Keith Owens Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp> Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to '')
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c
index 93aa911646ad..aca054cc0552 100644
--- a/arch/i386/kernel/apic.c
+++ b/arch/i386/kernel/apic.c
@@ -129,6 +129,28 @@ static int modern_apic(void)
return lapic_get_version() >= 0x14;
+void apic_wait_icr_idle(void)
+ while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
+ cpu_relax();
+unsigned long safe_apic_wait_icr_idle(void)
+ unsigned long send_status;
+ int timeout;
+ timeout = 0;
+ do {
+ send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
+ if (!send_status)
+ break;
+ udelay(100);
+ } while (timeout++ < 1000);
+ return send_status;
* enable_NMI_through_LVT0 - enable NMI through local vector table 0