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author谢致邦 (XIE Zhibang) <Yeking@Red54.com>2017-06-01 18:41:34 +0800
committerPaul Burton <paul.burton@mips.com>2018-07-30 18:54:15 -0700
commit968dc5a0eaca707f8eb2fbad57d9fbbf3284541e (patch)
tree4520f3977b4e6e9ba5dcc195911f3d6f16f693c5 /arch/mips/Kconfig
parentMIPS: mscc: ocelot: add interrupt controller properties to GPIO controller (diff)
downloadlinux-dev-968dc5a0eaca707f8eb2fbad57d9fbbf3284541e.tar.xz
linux-dev-968dc5a0eaca707f8eb2fbad57d9fbbf3284541e.zip
MIPS: Loongson: Set Loongson32 to MIPS32R1
LS232 (Loonson 2-issue 32-bit, also called GS232 (Godson 2-issue 32-bit)) is the CPU core (microarchitecture) of Loongson 1A/1B/1C. According to "LS232 用户手册 (LS232 User Manual)", LS232 implements the MIPS32 Release 1 instruction set, and part of the MIPS32 Release 2 instruction set. In the manual, LS232 implements all of the MIPS32R2 instruction set except the FPU instructions, and LS232 also implements 5 FPU instructions of the MIPS32R2 instruction set: CEIL.L.fmt, CVT.L.fmt, FLOOR.L.fmt, TRUNC.L.fmt, and ROUND.L.fmt. But a bug of the DI instruction has been found during tests, the DI instruction can not disable interrupts in arch_local_irq_disable() with CONFIG_PREEMPT_NONE=y and CFLAGS='-mno-branch-likely' in some cases. [paul.burton@mips.com: - Remove the _MIPS_ISA redefinition to match the change made for the generic MIPSr1 CPUs by commit 344ebf09949c ("MIPS: Always use -march=<arch>, not -<arch> shortcuts").] Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/16155/ Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org
Diffstat (limited to '')
-rw-r--r--arch/mips/Kconfig8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c95eb5ad0d96..642a56e2a1ea 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1424,7 +1424,8 @@ config CPU_LOONGSON1B
select LEDS_GPIO_REGISTER
help
The Loongson 1B is a 32-bit SoC, which implements the MIPS32
- release 2 instruction set.
+ Release 1 instruction set and part of the MIPS32 Release 2
+ instruction set.
config CPU_LOONGSON1C
bool "Loongson 1C"
@@ -1433,7 +1434,8 @@ config CPU_LOONGSON1C
select LEDS_GPIO_REGISTER
help
The Loongson 1C is a 32-bit SoC, which implements the MIPS32
- release 2 instruction set.
+ Release 1 instruction set and part of the MIPS32 Release 2
+ instruction set.
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
@@ -1833,7 +1835,7 @@ config CPU_LOONGSON2
config CPU_LOONGSON1
bool
select CPU_MIPS32
- select CPU_MIPSR2
+ select CPU_MIPSR1
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM