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authorJiaxun Yang <jiaxun.yang@flygoat.com>2020-01-13 18:14:59 +0800
committerPaul Burton <paulburton@kernel.org>2020-01-23 10:26:16 -0800
commitba9196d2e005a07dc616a044a57b47665efe133d (patch)
tree200ec1af1825ab3f938ddbabdfc4467080aee8bd /arch/mips/Kconfig
parentMIPS: OCTEON: octeon-irq: fix spelling mistake "to" -> "too" (diff)
downloadlinux-dev-ba9196d2e005a07dc616a044a57b47665efe133d.tar.xz
linux-dev-ba9196d2e005a07dc616a044a57b47665efe133d.zip
MIPS: Make DIEI support as a config option
DI(Disable Interrupt) and EI(Enable Interrupt) instructions is required by MIPSR2/MIPSR6, however, it appears to be buggy on some processors such as Loongson-3A1000. Thus we make it as a config option to allow disable it at compile time with CPU_MIPSR2 selected. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/Kconfig')
-rw-r--r--arch/mips/Kconfig9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 488ce71cce73..75fca0cee9a2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2084,12 +2084,14 @@ config CPU_MIPSR2
bool
default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
select CPU_HAS_RIXI
+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
select MIPS_SPRAM
config CPU_MIPSR6
bool
default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
select CPU_HAS_RIXI
+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
select HAVE_ARCH_BITREVERSE
select MIPS_ASID_BITS_VARIABLE
select MIPS_CRC_SUPPORT
@@ -2549,6 +2551,13 @@ config CPU_HAS_WB
config XKS01
bool
+config CPU_HAS_DIEI
+ depends on !CPU_DIEI_BROKEN
+ bool
+
+config CPU_DIEI_BROKEN
+ bool
+
config CPU_HAS_RIXI
bool