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| author |   Steven J. Hill <Steven.Hill@imgtec.com> | 2015-02-19 10:18:52 -0600 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2015-02-20 12:55:18 +0100 |
| commit | a5770df09541f88021390375f324b25124675355 (patch) | |
| tree | 96650246db3738bde279746626a859731df9e9a5 /arch/mips/mm/tlb-r4k.c | |
| parent | MIPS: Usage and cosmetic cleanups of page table bits. (diff) | |
| download | linux-dev-a5770df09541f88021390375f324b25124675355.tar.xz linux-dev-a5770df09541f88021390375f324b25124675355.zip | |
MIPS: Add set/clear CP0 macros for PageGrain register
Build set and clear macros for the PageGrain register.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9289/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/mips/mm/tlb-r4k.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index e90b2e899291..b2afa49beab0 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -485,11 +485,11 @@ static void r4k_tlb_configure(void) * Enable the no read, no exec bits, and enable large virtual * address. */ - u32 pg = PG_RIE | PG_XIE; #ifdef CONFIG_64BIT - pg |= PG_ELPA; + set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA); +#else + set_c0_pagegrain(PG_RIE | PG_XIE); #endif - write_c0_pagegrain(pg); } temp_tlb_entry = current_cpu_data.tlbsize - 1; |