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authorAaro Koskinen <aaro.koskinen@iki.fi>2019-02-05 00:41:45 +0200
committerPaul Burton <paul.burton@mips.com>2019-02-07 15:22:30 -0800
commit565485b8b5745946a303673873acd91de63b0657 (patch)
tree7eeddaa866e0dc63e490a05c59d0f55603e2f29e /arch/mips
parentMIPS: Delete unused flush_cache_sigtramp() (diff)
downloadlinux-dev-565485b8b5745946a303673873acd91de63b0657.tar.xz
linux-dev-565485b8b5745946a303673873acd91de63b0657.zip
MIPS: OCTEON: add fixed-link nodes to in-kernel device tree
Currently OCTEON ethernet falls back to phyless operation on boards where we have no known PHY address or a fixed-link node. Add fixed-link support for boards that need it, so we can clean up the platform code and ethernet driver from some legacy code. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts8
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c24
2 files changed, 32 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
index 0fa3dd1819ff..1c50cca4ea53 100644
--- a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
+++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
@@ -180,10 +180,18 @@
ethernet@0 {
phy-handle = <&phy2>;
cavium,alt-phy-handle = <&phy100>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
};
ethernet@1 {
phy-handle = <&phy3>;
cavium,alt-phy-handle = <&phy101>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
};
ethernet@2 {
phy-handle = <&phy4>;
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 1f9ba60f7375..b4073750822d 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -458,6 +458,23 @@ static bool __init octeon_has_88e1145(void)
!OCTEON_IS_MODEL(OCTEON_CN56XX);
}
+static bool __init octeon_has_fixed_link(int ipd_port)
+{
+ switch (cvmx_sysinfo_get()->board_type) {
+ case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
+ case CVMX_BOARD_TYPE_CUST_NB5:
+ case CVMX_BOARD_TYPE_EBH3100:
+ /* Port 1 on these boards is always gigabit. */
+ return ipd_port == 1;
+ case CVMX_BOARD_TYPE_BBGW_REF:
+ /* Ports 0 and 1 connect to the switch. */
+ return ipd_port == 0 || ipd_port == 1;
+ }
+ return false;
+}
+
static void __init octeon_fdt_set_phy(int eth, int phy_addr)
{
const __be32 *phy_handle;
@@ -592,6 +609,7 @@ static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
int eth;
int phy_addr;
int ipd_port;
+ int fixed_link;
snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
@@ -609,6 +627,12 @@ static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
octeon_fdt_set_phy(eth, phy_addr);
+
+ fixed_link = fdt_subnode_offset(initial_boot_params, eth, "fixed-link");
+ if (fixed_link < 0)
+ WARN_ON(octeon_has_fixed_link(ipd_port));
+ else if (!octeon_has_fixed_link(ipd_port))
+ fdt_nop_node(initial_boot_params, fixed_link);
}
static void __init octeon_fdt_pip_iface(int pip, int idx)