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authorVincent Chen <vincentc@andestech.com>2018-11-22 11:14:36 +0800
committerGreentime Hu <greentime@andestech.com>2018-11-22 18:13:27 +0800
commit44e92e0364adfd7b6759084e02a550d06336d896 (patch)
tree4fb8af79a5ce25f9467bdc22f44e67f6ae42b6d6 /arch/nds32/math-emu/fpuemu.c
parentnds32: Support FP emulation (diff)
downloadlinux-dev-44e92e0364adfd7b6759084e02a550d06336d896.tar.xz
linux-dev-44e92e0364adfd7b6759084e02a550d06336d896.zip
nds32: support denormalized result through FP emulator
Currently, the nds32 FPU dose not support the arithmetic of denormalized number. When the nds32 FPU finds the result of the instruction is a denormlized number, the nds32 FPU considers it to be an underflow condition and rounds the result to an appropriate number. It may causes some loss of precision. This commit proposes a solution to re-execute the instruction by the FPU emulator to enhance the precision. To transfer calculations from user space to kernel space, this feature will enable the underflow exception trap by default. Enabling this feature may cause some side effects: 1. Performance loss due to extra FPU exception 2. Need another scheme to control real underflow trap A new parameter, UDF_trap, which is belong to FPU context is used to control underflow trap. User can configure this feature via CONFIG_SUPPORT_DENORMAL_ARITHMETIC Signed-off-by: Vincent Chen <vincentc@andestech.com> Acked-by: Greentime Hu <greentime@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com>
Diffstat (limited to '')
-rw-r--r--arch/nds32/math-emu/fpuemu.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/nds32/math-emu/fpuemu.c b/arch/nds32/math-emu/fpuemu.c
index 2a01333d6e5f..75cf1643fa78 100644
--- a/arch/nds32/math-emu/fpuemu.c
+++ b/arch/nds32/math-emu/fpuemu.c
@@ -304,7 +304,12 @@ static int fpu_emu(struct fpu_struct *fpu_reg, unsigned long insn)
/*
* If an exception is required, generate a tidy SIGFPE exception.
*/
+#if IS_ENABLED(CONFIG_SUPPORT_DENORMAL_ARITHMETIC)
+ if (((fpu_reg->fpcsr << 5) & fpu_reg->fpcsr & FPCSR_mskALLE_NO_UDFE) ||
+ ((fpu_reg->fpcsr & FPCSR_mskUDF) && (fpu_reg->UDF_trap)))
+#else
if ((fpu_reg->fpcsr << 5) & fpu_reg->fpcsr & FPCSR_mskALLE)
+#endif
return SIGFPE;
return 0;
}