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authorNicholas Piggin <npiggin@gmail.com>2019-03-07 05:28:31 +0800
committerLey Foon Tan <ley.foon.tan@intel.com>2019-03-07 06:00:48 +0800
commit21e6bff5e0ef0033d776e64c40e6873d7c75e74b (patch)
tree501dd4adec10abc825735b5d44bcdebc8c721cd5 /arch/nios2/include/asm/tlbflush.h
parentnios2: update_mmu_cache preload the TLB with the new PTE (diff)
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nios2: Fix update_mmu_cache preload the TLB with the new PTE
There is a bug in the TLB preload caused by the pid not being shifted to the correct location in tlbmisc register. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Tested-by: Guenter Roeck <linux@roeck-us.net>
Diffstat (limited to 'arch/nios2/include/asm/tlbflush.h')
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