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authorJohn David Anglin <dave.anglin@bell.net>2018-08-05 13:30:31 -0400
committerHelge Deller <deller@gmx.de>2018-08-08 22:13:32 +0200
commitfedb8da96355f5f64353625bf96dc69423ad1826 (patch)
tree36c305623c2a88863801b2f6b5f407af392099eb /arch/parisc/kernel/pacache.S
parentparisc: Enable CONFIG_MLONGCALLS by default (diff)
downloadlinux-dev-fedb8da96355f5f64353625bf96dc69423ad1826.tar.xz
linux-dev-fedb8da96355f5f64353625bf96dc69423ad1826.zip
parisc: Define mb() and add memory barriers to assembler unlock sequences
For years I thought all parisc machines executed loads and stores in order. However, Jeff Law recently indicated on gcc-patches that this is not correct. There are various degrees of out-of-order execution all the way back to the PA7xxx processor series (hit-under-miss). The PA8xxx series has full out-of-order execution for both integer operations, and loads and stores. This is described in the following article: http://web.archive.org/web/20040214092531/http://www.cpus.hp.com/technical_references/advperf.shtml For this reason, we need to define mb() and to insert a memory barrier before the store unlocking spinlocks. This ensures that all memory accesses are complete prior to unlocking. The ldcw instruction performs the same function on entry. Signed-off-by: John David Anglin <dave.anglin@bell.net> Cc: stable@vger.kernel.org # 4.0+ Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc/kernel/pacache.S')
-rw-r--r--arch/parisc/kernel/pacache.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S
index 22e6374ece44..97451e67d35b 100644
--- a/arch/parisc/kernel/pacache.S
+++ b/arch/parisc/kernel/pacache.S
@@ -353,6 +353,7 @@ ENDPROC_CFI(flush_data_cache_local)
.macro tlb_unlock la,flags,tmp
#ifdef CONFIG_SMP
ldi 1,\tmp
+ sync
stw \tmp,0(\la)
mtsm \flags
#endif