diff options
| author |   Nicholas Piggin <npiggin@gmail.com> | 2019-10-02 16:00:21 +1000 |
|---|---|---|
| committer |   Paul Mackerras <paulus@ozlabs.org> | 2019-10-22 16:29:02 +1100 |
| commit | 9ee6471eb9d43114ba4f0de3e0f483bf6fb2a906 (patch) | |
| tree | d636a14cee59737d5a885066791491554fe45003 /arch/powerpc/include/asm/reg.h | |
| parent | KVM: PPC: Book3S HV: XIVE: Allow userspace to set the # of VPs (diff) | |
| download | linux-dev-9ee6471eb9d43114ba4f0de3e0f483bf6fb2a906.tar.xz linux-dev-9ee6471eb9d43114ba4f0de3e0f483bf6fb2a906.zip | |
KVM: PPC: Book3S: Define and use SRR1_MSR_BITS
Acked-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Diffstat (limited to 'arch/powerpc/include/asm/reg.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index b3cbb1136bce..75c7e95a321b 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -748,6 +748,18 @@ #define SPRN_USPRG7 0x107 /* SPRG7 userspace read */ #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ + +#ifdef CONFIG_PPC_BOOK3S +/* + * Bits loaded from MSR upon interrupt. + * PPC (64-bit) bits 33-36,42-47 are interrupt dependent, the others are + * loaded from MSR. The exception is that SRESET and MCE do not always load + * bit 62 (RI) from MSR. Don't use PPC_BITMASK for this because 32-bit uses + * it. + */ +#define SRR1_MSR_BITS (~0x783f0000UL) +#endif + #define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ #define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */ #define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */ |