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| author |   Christophe Leroy <christophe.leroy@c-s.fr> | 2019-12-02 07:57:31 +0000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2020-01-23 21:31:15 +1100 |
| commit | 2c29eef9fc6f61cfb81b54683be8f116dac80e7a (patch) | |
| tree | 952174262ff04fff05c622d9c8f79673947b7fe1 /arch/powerpc/kernel/vdso32/cacheflush.S | |
| parent | powerpc/vdso32: inline __get_datapage() (diff) | |
| download | linux-dev-2c29eef9fc6f61cfb81b54683be8f116dac80e7a.tar.xz linux-dev-2c29eef9fc6f61cfb81b54683be8f116dac80e7a.zip | |
powerpc/vdso32: Don't read cache line size from the datapage on PPC32.
On PPC32, the cache lines have a fixed size known at build time.
Don't read it from the datapage.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/dfa7b35e27e01964fcda84bf1ed8b2b31cf93826.1575273217.git.christophe.leroy@c-s.fr
Diffstat (limited to '')
| -rw-r--r-- | arch/powerpc/kernel/vdso32/cacheflush.S | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/vdso32/cacheflush.S b/arch/powerpc/kernel/vdso32/cacheflush.S index d178ec8c279d..3440ddf21c8b 100644 --- a/arch/powerpc/kernel/vdso32/cacheflush.S +++ b/arch/powerpc/kernel/vdso32/cacheflush.S @@ -10,6 +10,7 @@ #include <asm/vdso.h> #include <asm/vdso_datapage.h> #include <asm/asm-offsets.h> +#include <asm/cache.h> .text @@ -23,28 +24,44 @@ */ V_FUNCTION_BEGIN(__kernel_sync_dicache) .cfi_startproc +#ifdef CONFIG_PPC64 mflr r12 .cfi_register lr,r12 get_datapage r10, r0 mtlr r12 +#endif +#ifdef CONFIG_PPC64 lwz r7,CFG_DCACHE_BLOCKSZ(r10) addi r5,r7,-1 +#else + li r5, L1_CACHE_BYTES - 1 +#endif andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ +#ifdef CONFIG_PPC64 lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10) srw. r8,r8,r9 /* compute line count */ +#else + srwi. r8, r8, L1_CACHE_SHIFT + mr r7, r6 +#endif crclr cr0*4+so beqlr /* nothing to do? */ mtctr r8 1: dcbst 0,r6 +#ifdef CONFIG_PPC64 add r6,r6,r7 +#else + addi r6, r6, L1_CACHE_BYTES +#endif bdnz 1b sync /* Now invalidate the instruction cache */ +#ifdef CONFIG_PPC64 lwz r7,CFG_ICACHE_BLOCKSZ(r10) addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ @@ -54,9 +71,15 @@ V_FUNCTION_BEGIN(__kernel_sync_dicache) srw. r8,r8,r9 /* compute line count */ crclr cr0*4+so beqlr /* nothing to do? */ +#endif mtctr r8 +#ifdef CONFIG_PPC64 2: icbi 0,r6 add r6,r6,r7 +#else +2: icbi 0, r7 + addi r7, r7, L1_CACHE_BYTES +#endif bdnz 2b isync li r3,0 |