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authorKim Phillips <kim.phillips@freescale.com>2007-11-05 12:15:51 -0600
committerKumar Gala <galak@kernel.crashing.org>2007-11-19 22:14:48 -0600
commit29a50a8bd04ce88efe530fad4d0e21d045c0f25a (patch)
treec19b8a37ed0c3eb9d5b2701c9db7dc2ad36a0b86 /arch/powerpc
parent[POWERPC] Document rgmii-rxid and rgmii-txid phy-connection-types (diff)
downloadlinux-dev-29a50a8bd04ce88efe530fad4d0e21d045c0f25a.tar.xz
linux-dev-29a50a8bd04ce88efe530fad4d0e21d045c0f25a.zip
[POWERPC] 83xx: Handle mpc8360 rev. 2.1 RGMII timing erratum
If on a rev. 2.1, adjust UCC clock and data timing characteristics as specified in the rev.2.1 erratum #2. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/platforms/83xx/mpc836x_mds.c31
1 files changed, 28 insertions, 3 deletions
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 0f3855c95ff5..0a722601a2f0 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -96,14 +96,39 @@ static void __init mpc836x_mds_setup_arch(void)
if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
!= NULL){
+ uint svid;
+
/* Reset the Ethernet PHY */
- bcsr_regs[9] &= ~0x20;
+#define BCSR9_GETHRST 0x20
+ clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
udelay(1000);
- bcsr_regs[9] |= 0x20;
+ setbits8(&bcsr_regs[9], BCSR9_GETHRST);
+
+ /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
+ svid = mfspr(SPRN_SVR);
+ if (svid == 0x80480021) {
+ void __iomem *immap;
+
+ immap = ioremap(get_immrbase() + 0x14a8, 8);
+
+ /*
+ * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+ * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+ */
+ setbits32(immap, 0x0c003000);
+
+ /*
+ * IMMR + 0x14AC[20:27] = 10101010
+ * (data delay for both UCC's)
+ */
+ clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
+
+ iounmap(immap);
+ }
+
iounmap(bcsr_regs);
of_node_put(np);
}
-
#endif /* CONFIG_QUICC_ENGINE */
}