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| author |   Kefeng Wang <wangkefeng.wang@huawei.com> | 2021-08-12 19:47:02 +0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmerdabbelt@google.com> | 2021-09-10 22:25:34 -0700 |
| commit | d5935537c8256fc63c77d5f4914dfd6e3ef43241 (patch) | |
| tree | 879e8965f6c8908490c48bd80d528a0cae81601e /arch/riscv/include/asm/elf.h | |
| parent | riscv: defconfig: enable NLS_CODEPAGE_437, NLS_ISO8859_1 (diff) | |
| download | linux-dev-d5935537c8256fc63c77d5f4914dfd6e3ef43241.tar.xz linux-dev-d5935537c8256fc63c77d5f4914dfd6e3ef43241.zip | |
riscv: Improve stack randomisation on RV64
This enlarges the bits availiable for stack randomisation on RV64 from
the default of 8MiB to 1GiB, to match arm64 and x86.
Also, update the documentation to reflect our support for stack
randomisation.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/riscv/include/asm/elf.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index f4b490cd0e5d..f53c40026c7a 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -42,6 +42,9 @@ */ #define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2) +#ifdef CONFIG_64BIT +#define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12)) +#endif /* * This yields a mask that user programs can use to figure out what * instruction set this CPU supports. This could be done in user space, |