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| author |   Dao Lu <daolu@rivosinc.com> | 2022-06-20 13:15:25 -0700 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-11 08:03:49 -0700 |
| commit | 8eb060e10185cfc97ef0200d197ec246ba0f9f8c (patch) | |
| tree | 5d72c5ef54b14b6b84b202ceae056cb401cf4284 /arch/riscv/kernel/cpufeature.c | |
| parent | riscv: implement Zicbom-based CMO instructions + the t-head variant (diff) | |
| download | linux-dev-8eb060e10185cfc97ef0200d197ec246ba0f9f8c.tar.xz linux-dev-8eb060e10185cfc97ef0200d197ec246ba0f9f8c.zip | |
arch/riscv: add Zihintpause support
Implement support for the ZiHintPause extension.
The PAUSE instruction is a HINT that indicates the current hart’s rate
of instruction retirement should be temporarily reduced or paused.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Dao Lu <daolu@rivosinc.com>
[Palmer: Some minor merge conflicts.]
Link: https://lore.kernel.org/all/20220620201530.3929352-1-daolu@rivosinc.com/
Link: https://lore.kernel.org/all/20220811053356.17375-1-palmer@rivosinc.com/
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/riscv/kernel/cpufeature.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f914e8da157a..c233fbc5b873 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -202,6 +202,7 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); } #undef SET_ISA_EXT_MAP } |