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authorPaul Mundt <lethal@linux-sh.org>2006-12-25 10:19:56 +0900
committerPaul Mundt <lethal@linux-sh.org>2007-02-13 10:54:45 +0900
commit11c1965687b0a472add948d4240dfe65a2fcb298 (patch)
tree69a71a34591bbdc6339dbe72de36819479f96198 /arch/sh/kernel/cpu/sh2/probe.c
parentsh: Use a per-cpu ASID cache. (diff)
downloadlinux-dev-11c1965687b0a472add948d4240dfe65a2fcb298.tar.xz
linux-dev-11c1965687b0a472add948d4240dfe65a2fcb298.zip
sh: Fixup cpu_data references for the non-boot CPUs.
There are a lot of bogus cpu_data-> references that only end up working for the boot CPU, convert these to current_cpu_data to fixup SMP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to '')
-rw-r--r--arch/sh/kernel/cpu/sh2/probe.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index ba527d9b5024..108e81b682ed 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -18,27 +18,27 @@
int __init detect_cpu_and_cache_system(void)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7604)
- cpu_data->type = CPU_SH7604;
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.way_incr = (1<<10);
- cpu_data->dcache.sets = 64;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.type = CPU_SH7604;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.way_incr = (1<<10);
+ current_cpu_data.dcache.sets = 64;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
- cpu_data->type = CPU_SH7619;
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.way_incr = (1<<12);
- cpu_data->dcache.sets = 256;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.type = CPU_SH7619;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.way_incr = (1<<12);
+ current_cpu_data.dcache.sets = 256;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
#endif
/*
* SH-2 doesn't have separate caches
*/
- cpu_data->dcache.flags |= SH_CACHE_COMBINED;
- cpu_data->icache = cpu_data->dcache;
+ current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+ current_cpu_data.icache = current_cpu_data.dcache;
return 0;
}