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authorRich Felker <dalias@libc.org>2016-04-22 23:29:13 +0000
committerRich Felker <dalias@libc.org>2016-08-05 03:29:32 +0000
commit834da197058bebcb343320dafb8b62d416d4038c (patch)
tree86014306af44c06b216683dfbc20aa2a8e997b18 /arch/sh/kernel/cpu/sh2/probe.c
parentsh: add support for J-Core J2 processor (diff)
downloadlinux-dev-834da197058bebcb343320dafb8b62d416d4038c.tar.xz
linux-dev-834da197058bebcb343320dafb8b62d416d4038c.zip
sh: add AT_HWCAP flag for J-Core cas.l instruction
The J-Core cpu has, as an ISA extension, an atomic compare-and-swap instruction cas.l which applications need to use (instead the imask or gusa atomic models, which are fundamentally limited to UP) for synchronization in order to be compatible with SMP systems. Provide a hwcap flag so that it's possible to do runtime selection and support both. Signed-off-by: Rich Felker <dalias@libc.org>
Diffstat (limited to '')
-rw-r--r--arch/sh/kernel/cpu/sh2/probe.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index 152184007964..4205f6d42b69 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -57,6 +57,8 @@ void __ref cpu_probe(void)
boot_cpu_data.dcache.entry_shift = 5;
boot_cpu_data.dcache.linesz = 32;
boot_cpu_data.dcache.flags = 0;
+
+ boot_cpu_data.flags |= CPU_HAS_CAS_L;
#else
/*
* SH-2 doesn't have separate caches