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authorPaul Mundt <lethal@linux-sh.org>2007-09-27 18:18:39 +0900
committerPaul Mundt <lethal@linux-sh.org>2007-09-27 18:18:39 +0900
commitcb7af21f7d370edb3a6a6d3e15cb17c8fd61591e (patch)
tree9042e4b322593adc3864b28a8c0899d7af7a52da /arch/sh/kernel/cpu/sh2/probe.c
parentsh: Support extended mode TLB on SH-X3. (diff)
downloadlinux-dev-cb7af21f7d370edb3a6a6d3e15cb17c8fd61591e.tar.xz
linux-dev-cb7af21f7d370edb3a6a6d3e15cb17c8fd61591e.zip
sh: Use boot_cpu_data for CPU probe.
This moves off of smp_processor_id() and only sets the probe information for the boot CPU directly. This will be copied out for the secondaries, so there's no reason to do this each time. This also allows for some header tidying. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to '')
-rw-r--r--arch/sh/kernel/cpu/sh2/probe.c19
1 files changed, 9 insertions, 10 deletions
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index abbf17427e52..5916d9096b99 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -10,26 +10,25 @@
* for more details.
*/
#include <linux/init.h>
-#include <linux/smp.h>
#include <asm/processor.h>
#include <asm/cache.h>
int __init detect_cpu_and_cache_system(void)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
- current_cpu_data.type = CPU_SH7619;
- current_cpu_data.dcache.ways = 4;
- current_cpu_data.dcache.way_incr = (1<<12);
- current_cpu_data.dcache.sets = 256;
- current_cpu_data.dcache.entry_shift = 4;
- current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
- current_cpu_data.dcache.flags = 0;
+ boot_cpu_data.type = CPU_SH7619;
+ boot_cpu_data.dcache.ways = 4;
+ boot_cpu_data.dcache.way_incr = (1<<12);
+ boot_cpu_data.dcache.sets = 256;
+ boot_cpu_data.dcache.entry_shift = 4;
+ boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ boot_cpu_data.dcache.flags = 0;
#endif
/*
* SH-2 doesn't have separate caches
*/
- current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
- current_cpu_data.icache = current_cpu_data.dcache;
+ boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+ boot_cpu_data.icache = boot_cpu_data.dcache;
return 0;
}