path: root/arch/sparc/kernel/head_64.S
diff options
authorDavid S. Miller <davem@davemloft.net>2012-10-05 13:45:26 -0700
committerDavid S. Miller <davem@davemloft.net>2012-10-05 13:45:26 -0700
commit9f825962efdee5c2b22ac1f6cda50056336c06e1 (patch)
tree0fc01939390a964c843456ecabece53a54856191 /arch/sparc/kernel/head_64.S
parentsparc64: Fix strace hiccups when force_successful_syscall() triggers. (diff)
sparc64: Niagara-4 bzero/memset, plus use MRU stores in page copy.
This adds optimized memset/bzero/page-clear routines for Niagara-4. We basically can do what powerpc has been able to do for a decade (via the "dcbz" instruction), which is use cache line clearing stores for bzero and memsets with a 'c' argument of zero. As long as we make the cache initializing store to each 32-byte subblock of the L2 cache line, it works. As with other Niagara-4 optimized routines, the key is to make sure to avoid any usage of the %asi register, as reads and writes to it cost at least 50 cycles. For the user clear cases, we don't use these new routines, we use the Niagara-1 variants instead. Those have to use %asi in an unavoidable way. A Niagara-4 8K page clear costs just under 600 cycles. Add definitions of the MRU variants of the cache initializing store ASIs. By default, cache initializing stores install the line as Least Recently Used. If we know we're going to use the data immediately (which is true for page copies and clears) we can use the Most Recently Used variant, to decrease the likelyhood of the lines being evicted before they get used. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel/head_64.S')
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index ee5dcced2499..2feb15c35d9e 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -576,7 +576,7 @@ niagara_tlb_fixup:
call niagara4_patch_copyops
- call niagara_patch_bzero
+ call niagara4_patch_bzero
call niagara4_patch_pageops