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authorSam Ravnborg <sam@ravnborg.org>2014-05-16 23:25:46 +0200
committerDavid S. Miller <davem@davemloft.net>2014-05-18 19:01:28 -0700
commit347b0cf022a8da1b4517acc7ea310a27ca2cf7ef (patch)
tree791c0763089913c8ae4aedfa8f06a44ea2d5ddae /arch/sparc/math-emu
parentsparc32: fix sparse warnings in sys_sparc_32.c (diff)
downloadlinux-dev-347b0cf022a8da1b4517acc7ea310a27ca2cf7ef.tar.xz
linux-dev-347b0cf022a8da1b4517acc7ea310a27ca2cf7ef.zip
sparc32: remove cast from output constraints in math asm statements
The following asm statements generated a sparse warning: asm("addcc \n\t" : "=r" (((USItype)(r2))) warning: asm output is not an lvalue When asking on the sparse mailing list Linus replyed: " Those casts to (USItype) are all pointless to begin with (since the values are of that type already!) and they mean that the expression isn't something you can assign to (lvalue). " In the math emulation code drop all casts in the output parts of the asm statements. This fixes a lot of "warning: asm output is not an lvalue" sparse warnings in math_32.c. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/math-emu')
-rw-r--r--arch/sparc/math-emu/sfp-util_32.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/sparc/math-emu/sfp-util_32.h b/arch/sparc/math-emu/sfp-util_32.h
index d1b2aff3c259..bb587d5f3d9d 100644
--- a/arch/sparc/math-emu/sfp-util_32.h
+++ b/arch/sparc/math-emu/sfp-util_32.h
@@ -4,20 +4,20 @@
#include <asm/byteorder.h>
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
- __asm__ ("addcc %r4,%5,%1\n\t" \
+ __asm__ ("addcc %r4,%5,%1\n\t" \
"addx %r2,%3,%0\n" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%rJ" ((USItype)(ah)), \
"rI" ((USItype)(bh)), \
"%rJ" ((USItype)(al)), \
"rI" ((USItype)(bl)) \
: "cc")
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
- __asm__ ("subcc %r4,%5,%1\n\t" \
+ __asm__ ("subcc %r4,%5,%1\n\t" \
"subx %r2,%3,%0\n" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "rJ" ((USItype)(ah)), \
"rI" ((USItype)(bh)), \
"rJ" ((USItype)(al)), \
@@ -65,8 +65,8 @@
"mulscc %%g1,0,%%g1\n\t" \
"add %%g1,%%g2,%0\n\t" \
"rd %%y,%1\n" \
- : "=r" ((USItype)(w1)), \
- "=r" ((USItype)(w0)) \
+ : "=r" (w1), \
+ "=r" (w0) \
: "%rI" ((USItype)(u)), \
"r" ((USItype)(v)) \
: "%g1", "%g2", "cc")
@@ -98,8 +98,8 @@
"sub %1,%2,%1\n\t" \
"3: xnor %0,0,%0\n\t" \
"! End of inline udiv_qrnnd\n" \
- : "=&r" ((USItype)(q)), \
- "=&r" ((USItype)(r)) \
+ : "=&r" (q), \
+ "=&r" (r) \
: "r" ((USItype)(d)), \
"1" ((USItype)(n1)), \
"0" ((USItype)(n0)) : "%g1", "cc")