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authorchris hyser <chris.hyser@oracle.com>2016-09-28 12:19:50 -0700
committerDavid S. Miller <davem@davemloft.net>2016-10-06 01:44:51 -0400
commitaa7bde1a8b49391d34f17905a04c3acf7770283d (patch)
tree8211bfaa3f0a1079db760f96f9d7ff277f996f62 /arch/sparc/prom
parentsparc64: Enable PCI IOMMU version 2 API (diff)
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sparc64: Enable setting "relaxed ordering" in IOMMU mappings
Enable relaxed ordering for memory writes in IOMMU TSB entry from dma_4v_alloc_coherent(), dma_4v_map_page() and dma_4v_map_sg() when dma_attrs DMA_ATTR_WEAK_ORDERING is set. This requires PCI IOMMU I/O Translation Services version 2.0 API. Many PCIe devices allow enabling relaxed-ordering (memory writes bypassing other memory writes) for various DMA buffers. A notable exception is the Mellanox mlx4 IB adapter. Due to the nature of x86 HW this appears to have little performance impact there. On SPARC HW however, this results in major performance degradation getting only about 3Gbps. Enabling RO in the IOMMU entries corresponding to mlx4 data buffers increases the throughput to about 13 Gbps. Orabug: 19245907 Signed-off-by: Chris Hyser <chris.hyser@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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