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| author |   Andi Kleen <ak@linux.intel.com> | 2017-08-31 14:46:30 -0700 |
|---|---|---|
| committer |   Ingo Molnar <mingo@kernel.org> | 2017-12-17 13:55:17 +0100 |
| commit | 2fe1bc1f501d55e5925b4035bcd85781adc76c63 (patch) | |
| tree | 5c8d65bd583d098850e837ed489fc3827b272bb7 /arch/um/include/asm/Kbuild | |
| parent | x86: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMD (diff) | |
| download | linux-dev-2fe1bc1f501d55e5925b4035bcd85781adc76c63.tar.xz linux-dev-2fe1bc1f501d55e5925b4035bcd85781adc76c63.zip | |
perf/x86: Enable free running PEBS for REGS_USER/INTR
[ Note, this is a Git cherry-pick of the following commit:
a47ba4d77e12 ("perf/x86: Enable free running PEBS for REGS_USER/INTR")
... for easier x86 PTI code testing and back-porting. ]
Currently free running PEBS is disabled when user or interrupt
registers are requested. Most of the registers are actually
available in the PEBS record and can be supported.
So we just need to check for the supported registers and then
allow it: it is all except for the segment register.
For user registers this only works when the counter is limited
to ring 3 only, so this also needs to be checked.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20170831214630.21892-1-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions