diff options
| author |   Andi Kleen <ak@linux.intel.com> | 2016-12-08 16:14:17 -0800 |
|---|---|---|
| committer |   Ingo Molnar <mingo@kernel.org> | 2016-12-11 13:06:09 +0100 |
| commit | b0c1ef52959582144bbea9a2b37db7f4c9e399f7 (patch) | |
| tree | 4e64446d543139c7177d08b9a060e2a340d3f400 /arch/x86/events/perf_event.h | |
| parent | Merge branch 'linus' into perf/core, to pick up fixes (diff) | |
| download | linux-dev-b0c1ef52959582144bbea9a2b37db7f4c9e399f7.tar.xz linux-dev-b0c1ef52959582144bbea9a2b37db7f4c9e399f7.zip | |
perf/x86: Fix exclusion of BTS and LBR for Goldmont
An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: alexander.shishkin@intel.com
Cc: kan.liang@intel.com
Cc: <stable@vger.kernel.org>
Fixes: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
Link: http://lkml.kernel.org/r/20161209001417.4713-1-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/x86/events/perf_event.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index a77ee026643d..bcbb1d2ae10b 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -604,7 +604,7 @@ struct x86_pmu { u64 lbr_sel_mask; /* LBR_SELECT valid bits */ const int *lbr_sel_map; /* lbr_select mappings */ bool lbr_double_abort; /* duplicated lbr aborts */ - bool lbr_pt_coexist; /* LBR may coexist with PT */ + bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ /* * Intel PT/LBR/BTS are exclusive |