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| author |   Peter Zijlstra <peterz@infradead.org> | 2022-06-14 23:15:54 +0200 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2022-06-27 10:33:59 +0200 |
| commit | c779bc1a9002fa474175b80e72b85c9bf628abb0 (patch) | |
| tree | e79fbab2ca5f15aad4a76200cd56c6ae899dfd67 /arch/x86/include | |
| parent | x86/entry: Add kernel IBRS implementation (diff) | |
| download | linux-dev-c779bc1a9002fa474175b80e72b85c9bf628abb0.tar.xz linux-dev-c779bc1a9002fa474175b80e72b85c9bf628abb0.zip | |
x86/bugs: Optimize SPEC_CTRL MSR writes
When changing SPEC_CTRL for user control, the WRMSR can be delayed
until return-to-user when KERNEL_IBRS has been enabled.
This avoids an MSR write during context switch.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/nospec-branch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index bac243da5130..b6abf0c6b41d 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -253,7 +253,7 @@ static inline void indirect_branch_prediction_barrier(void) /* The Intel SPEC CTRL MSR base value cache */ extern u64 x86_spec_ctrl_base; -extern void write_spec_ctrl_current(u64 val); +extern void write_spec_ctrl_current(u64 val, bool force); /* * With retpoline, we must use IBRS to restrict branch prediction |