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authorMark Brown <broonie@kernel.org>2015-03-10 10:37:02 +0000
committerMark Brown <broonie@kernel.org>2015-03-10 10:37:02 +0000
commiteb5bc2a213f96bd43b5f00a625acb0c669613645 (patch)
tree6093a86c9e704ebfed54adb426ff3079a428da93 /arch/x86/kernel/cpu/mcheck/p5.c
parentASoC: rt5670: Check sysclk source by private data (diff)
parentLinux 4.0-rc3 (diff)
downloadlinux-dev-eb5bc2a213f96bd43b5f00a625acb0c669613645.tar.xz
linux-dev-eb5bc2a213f96bd43b5f00a625acb0c669613645.zip
Merge tag 'v4.0-rc3' into asoc-rt5670
Linux 4.0-rc3 Conflicts: sound/soc/codecs/rt5670.c
Diffstat (limited to 'arch/x86/kernel/cpu/mcheck/p5.c')
-rw-r--r--arch/x86/kernel/cpu/mcheck/p5.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/p5.c b/arch/x86/kernel/cpu/mcheck/p5.c
index a3042989398c..737b0ad4e61a 100644
--- a/arch/x86/kernel/cpu/mcheck/p5.c
+++ b/arch/x86/kernel/cpu/mcheck/p5.c
@@ -8,6 +8,8 @@
#include <linux/smp.h>
#include <asm/processor.h>
+#include <asm/traps.h>
+#include <asm/tlbflush.h>
#include <asm/mce.h>
#include <asm/msr.h>
@@ -17,8 +19,11 @@ int mce_p5_enabled __read_mostly;
/* Machine check handler for Pentium class Intel CPUs: */
static void pentium_machine_check(struct pt_regs *regs, long error_code)
{
+ enum ctx_state prev_state;
u32 loaddr, hi, lotype;
+ prev_state = ist_enter(regs);
+
rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
@@ -33,6 +38,8 @@ static void pentium_machine_check(struct pt_regs *regs, long error_code)
}
add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
+
+ ist_exit(regs, prev_state);
}
/* Set up machine check reporting for processors with Intel style MCE: */
@@ -59,7 +66,7 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
"Intel old style machine check architecture supported.\n");
/* Enable MCE: */
- set_in_cr4(X86_CR4_MCE);
+ cr4_set_bits(X86_CR4_MCE);
printk(KERN_INFO
"Intel old style machine check reporting enabled on CPU#%d.\n",
smp_processor_id());