diff options
| author |   Chao Peng <chao.p.peng@linux.intel.com> | 2018-10-24 16:05:12 +0800 |
|---|---|---|
| committer |   Paolo Bonzini <pbonzini@redhat.com> | 2018-12-21 11:28:35 +0100 |
| commit | 2ef444f1600bfc2d8522df0f537aafef79befa7e (patch) | |
| tree | 1bdc097495a69ed493a21ef07cb07e77db0da902 /arch/x86/kvm/vmx/vmx.h | |
| parent | KVM: x86: Add Intel Processor Trace cpuid emulation (diff) | |
| download | linux-dev-2ef444f1600bfc2d8522df0f537aafef79befa7e.tar.xz linux-dev-2ef444f1600bfc2d8522df0f537aafef79befa7e.zip | |
KVM: x86: Add Intel PT context switch for each vcpu
Load/Store Intel Processor Trace register in context switch.
MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS.
In Host-Guest mode, we need load/resore PT MSRs only when PT
is enabled in guest.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/x86/kvm/vmx/vmx.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 86eb9c887386..dd3b9ab90556 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -66,6 +66,25 @@ struct pi_desc { u32 rsvd[6]; } __aligned(64); +#define RTIT_ADDR_RANGE 4 + +struct pt_ctx { + u64 ctl; + u64 status; + u64 output_base; + u64 output_mask; + u64 cr3_match; + u64 addr_a[RTIT_ADDR_RANGE]; + u64 addr_b[RTIT_ADDR_RANGE]; +}; + +struct pt_desc { + u64 ctl_bitmask; + u32 addr_range; + u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; + struct pt_ctx host; + struct pt_ctx guest; +}; /* * The nested_vmx structure is part of vcpu_vmx, and holds information we need @@ -249,6 +268,8 @@ struct vcpu_vmx { u64 msr_ia32_feature_control; u64 msr_ia32_feature_control_valid_bits; u64 ept_pointer; + + struct pt_desc pt_desc; }; enum ept_pointers_status { |