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authorNickey Yang <nickey.yang@rock-chips.com>2017-09-26 15:55:22 +0800
committerHeiko Stuebner <heiko@sntech.de>2017-09-26 15:59:17 +0200
commit0bc15d85d97d44e8979ff91d0c1fbafe6fd4172c (patch)
tree22f0eb6808d26ab5562aca9b05df1bc2c97f10e4 /arch
parentarm64: dts: rockchip: Correct MIPI DPHY PLL clock on rk3399 (diff)
downloadlinux-dev-0bc15d85d97d44e8979ff91d0c1fbafe6fd4172c.tar.xz
linux-dev-0bc15d85d97d44e8979ff91d0c1fbafe6fd4172c.zip
arm64: dts: rockchip: add the grf clk for dw-mipi-dsi on rk3399
The clk of grf must be enabled before writing grf register for rk3399. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> [the grf clock is already part of the binding since march 2017] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 6aa43fd47148..ab7629c5b856 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1630,8 +1630,8 @@
reg = <0x0 0xff960000 0x0 0x8000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
- <&cru SCLK_DPHY_TX0_CFG>;
- clock-names = "ref", "pclk", "phy_cfg";
+ <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
+ clock-names = "ref", "pclk", "phy_cfg", "grf";
power-domains = <&power RK3399_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";