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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2017-09-04 12:48:43 +0300
committerVineet Gupta <vgupta@synopsys.com>2017-10-03 20:36:49 -0700
commitef833eab1ddec06982ea620086b03d67ef4ddf9b (patch)
tree6d96b27c0b4e90d107c7ecf5a0853364d01a9402 /arch
parentARC: [*defconfig] Reenable soft lock-up detector (diff)
downloadlinux-dev-ef833eab1ddec06982ea620086b03d67ef4ddf9b.tar.xz
linux-dev-ef833eab1ddec06982ea620086b03d67ef4ddf9b.zip
ARC: [plat-hsdk] use actual clk driver to manage cpu clk
With corresponding clk driver now merged upstream, switch to it. - core_clk now represent the PLL (vs. fixed clk before) - input_clk represent the clk signal src for PLL (basically xtal) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arc/boot/dts/hsdk.dts11
-rw-r--r--arch/arc/plat-hsdk/Kconfig3
2 files changed, 11 insertions, 3 deletions
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
index daeef4ab2df9..b922f3faf554 100644
--- a/arch/arc/boot/dts/hsdk.dts
+++ b/arch/arc/boot/dts/hsdk.dts
@@ -57,10 +57,10 @@
};
};
- core_clk: core-clk {
+ input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <500000000>;
+ clock-frequency = <33333333>;
};
cpu_intc: cpu-interrupt-controller {
@@ -102,6 +102,13 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core-clk@0 {
+ compatible = "snps,hsdk-core-pll-clock";
+ reg = <0x00 0x10>, <0x14B8 0x4>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
+ };
+
serial: serial@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
diff --git a/arch/arc/plat-hsdk/Kconfig b/arch/arc/plat-hsdk/Kconfig
index 5a6ed5afb009..bd08de4be75e 100644
--- a/arch/arc/plat-hsdk/Kconfig
+++ b/arch/arc/plat-hsdk/Kconfig
@@ -6,4 +6,5 @@
#
menuconfig ARC_SOC_HSDK
- bool "ARC HS Development Kit SOC"
+ bool "ARC HS Development Kit SOC"
+ select CLK_HSDK