path: root/arch
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authorFrank van Maarseveen <frankvm@frankvm.com>2005-09-09 13:01:46 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-09 13:57:29 -0700
commit99cc2192132ab28c495d015ed2e95dc29e2a27ad (patch)
tree4cc085c47f0824f4b028d6d31eab0f63765615c0 /arch
parent[PATCH] ppc32: make perfmon.o CONFIG_E500 specific (diff)
[PATCH] ppc32: Correct an instruction in the boot code
In the flush and invalidate bootcode on PPC4xx we were accidentally using the wrong instruction. Use cmplw, which reads from a register like we want. Signed-off-by: Tom Rini <trini@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ppc/boot/common/util.S b/arch/ppc/boot/common/util.S
index 47e641455bc5..c96c9f80521e 100644
--- a/arch/ppc/boot/common/util.S
+++ b/arch/ppc/boot/common/util.S
@@ -252,7 +252,7 @@ _GLOBAL(flush_instruction_cache)
1: dcbf r0,r3 # Flush the data cache
icbi r0,r3 # Invalidate the instruction cache
addi r3,r3,0x10 # Increment by one cache line
- cmplwi cr0,r3,r4 # Are we at the end yet?
+ cmplw cr0,r3,r4 # Are we at the end yet?
blt 1b # No, keep flushing and invalidating
/* Enable, invalidate and then disable the L1 icache/dcache. */