aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorMike Frysinger <michael.frysinger@analog.com>2007-11-21 16:12:12 +0800
committerBryan Wu <bryan.wu@analog.com>2007-11-21 16:12:12 +0800
commitc3a9f435ae1b1969736a6ca695dfbc508b917b65 (patch)
treedcd03b47fd0c6ba43e9f9304b343369d7cdd8c15 /arch
parentBlackfin arch: cleanup the cplb declares (diff)
downloadlinux-dev-c3a9f435ae1b1969736a6ca695dfbc508b917b65.tar.xz
linux-dev-c3a9f435ae1b1969736a6ca695dfbc508b917b65.zip
Blackfin arch: cplb and map header file cleanup
- remove duplicated defines for the BF561 - generalize L2 support (so that it works for BF54x) and mark it executable - add support for reading/executing the Boot ROM sections (since it has data/functions we may need at runtime) - and fixup names for each map Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to '')
-rw-r--r--arch/blackfin/kernel/cplbinit.c42
1 files changed, 26 insertions, 16 deletions
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c
index 959b510c5ffb..6320bc45fbba 100644
--- a/arch/blackfin/kernel/cplbinit.c
+++ b/arch/blackfin/kernel/cplbinit.c
@@ -64,7 +64,7 @@ static struct cplb_desc cplb_data[] = {
#else
.valid = 0,
#endif
- .name = "ZERO Pointer Saveguard",
+ .name = "Zero Pointer Guard Page",
},
{
.start = L1_CODE_START,
@@ -95,20 +95,20 @@ static struct cplb_desc cplb_data[] = {
.end = 0, /* dynamic */
.psize = 0,
.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
- .i_conf = SDRAM_IGENERIC,
- .d_conf = SDRAM_DGENERIC,
+ .i_conf = SDRAM_IGENERIC,
+ .d_conf = SDRAM_DGENERIC,
.valid = 1,
- .name = "SDRAM Kernel",
+ .name = "Kernel Memory",
},
{
.start = 0, /* dynamic */
.end = 0, /* dynamic */
.psize = 0,
.attr = INITIAL_T | SWITCH_T | D_CPLB,
- .i_conf = SDRAM_IGENERIC,
- .d_conf = SDRAM_DNON_CHBL,
+ .i_conf = SDRAM_IGENERIC,
+ .d_conf = SDRAM_DNON_CHBL,
.valid = 1,
- .name = "SDRAM RAM MTD",
+ .name = "uClinux MTD Memory",
},
{
.start = 0, /* dynamic */
@@ -117,7 +117,7 @@ static struct cplb_desc cplb_data[] = {
.attr = INITIAL_T | SWITCH_T | D_CPLB,
.d_conf = SDRAM_DNON_CHBL,
.valid = 1,
- .name = "SDRAM Uncached DMA ZONE",
+ .name = "Uncached DMA Zone",
},
{
.start = 0, /* dynamic */
@@ -127,7 +127,7 @@ static struct cplb_desc cplb_data[] = {
.i_conf = 0, /* dynamic */
.d_conf = 0, /* dynamic */
.valid = 1,
- .name = "SDRAM Reserved Memory",
+ .name = "Reserved Memory",
},
{
.start = ASYNC_BANK0_BASE,
@@ -136,14 +136,14 @@ static struct cplb_desc cplb_data[] = {
.attr = SWITCH_T | D_CPLB,
.d_conf = SDRAM_EBIU,
.valid = 1,
- .name = "ASYNC Memory",
+ .name = "Asynchronous Memory Banks",
},
{
-#if defined(CONFIG_BF561)
- .start = L2_SRAM,
- .end = L2_SRAM_END,
+#ifdef L2_START
+ .start = L2_START,
+ .end = L2_START + L2_LENGTH,
.psize = SIZE_1M,
- .attr = SWITCH_T | D_CPLB,
+ .attr = SWITCH_T | I_CPLB | D_CPLB,
.i_conf = L2_MEMORY,
.d_conf = L2_MEMORY,
.valid = 1,
@@ -151,7 +151,17 @@ static struct cplb_desc cplb_data[] = {
.valid = 0,
#endif
.name = "L2 Memory",
- }
+ },
+ {
+ .start = BOOT_ROM_START,
+ .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
+ .psize = SIZE_1M,
+ .attr = SWITCH_T | I_CPLB | D_CPLB,
+ .i_conf = SDRAM_IGENERIC,
+ .d_conf = SDRAM_DGENERIC,
+ .valid = 1,
+ .name = "On-Chip BootROM",
+ },
};
static u16 __init lock_kernel_check(u32 start, u32 end)
@@ -343,7 +353,7 @@ void __init generate_cpl_tables(void)
else
cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
- for (i = ZERO_P; i <= L2_MEM; i++) {
+ for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
if (!cplb_data[i].valid)
continue;