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author | James Morris <james.morris@microsoft.com> | 2018-09-04 11:35:54 -0700 |
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committer | James Morris <james.morris@microsoft.com> | 2018-09-04 11:35:54 -0700 |
commit | e42f6f9be4f83c537aa81b4c6239ea94ff5b29ce (patch) | |
tree | f956a5ea0e83fc6d0df3e64681e7bbc1f201f3ee /drivers/clk/meson/axg.h | |
parent | security/capabilities: remove check for -EINVAL (diff) | |
parent | Linux 4.19-rc2 (diff) | |
download | linux-dev-e42f6f9be4f83c537aa81b4c6239ea94ff5b29ce.tar.xz linux-dev-e42f6f9be4f83c537aa81b4c6239ea94ff5b29ce.zip |
Merge tag 'v4.19-rc2' into next-general
Sync to Linux 4.19-rc2 for downstream developers.
Diffstat (limited to '')
-rw-r--r-- | drivers/clk/meson/axg.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index b421df6a7ea0..1d04144a1b2c 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -16,6 +16,7 @@ * Register offsets from the data sheet must be multiplied by 4 before * adding them to the base address to get the right value. */ +#define HHI_MIPI_CNTL0 0x00 #define HHI_GP0_PLL_CNTL 0x40 #define HHI_GP0_PLL_CNTL2 0x44 #define HHI_GP0_PLL_CNTL3 0x48 @@ -127,8 +128,13 @@ #define CLKID_FCLK_DIV4_DIV 73 #define CLKID_FCLK_DIV5_DIV 74 #define CLKID_FCLK_DIV7_DIV 75 +#define CLKID_PCIE_PLL 76 +#define CLKID_PCIE_MUX 77 +#define CLKID_PCIE_REF 78 +#define CLKID_GEN_CLK_SEL 82 +#define CLKID_GEN_CLK_DIV 83 -#define NR_CLKS 76 +#define NR_CLKS 85 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/axg-clkc.h> |