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| author |   Giovanni Cabiddu <giovanni.cabiddu@intel.com> | 2021-12-16 09:13:14 +0000 |
|---|---|---|
| committer |   Herbert Xu <herbert@gondor.apana.org.au> | 2021-12-24 14:18:23 +1100 |
| commit | 4b44d28c715d3db2c8de1e4ec9ccfdf230001007 (patch) | |
| tree | 6cf7a701c2040a227515231273f443857ce2b0ba /drivers/crypto/qat/qat_common/icp_qat_hw.h | |
| parent | crypto: qat - set COMPRESSION capability for QAT GEN2 (diff) | |
| download | linux-dev-4b44d28c715d3db2c8de1e4ec9ccfdf230001007.tar.xz linux-dev-4b44d28c715d3db2c8de1e4ec9ccfdf230001007.zip | |
crypto: qat - extend crypto capability detection for 4xxx
Extended the capability detection logic for 4xxx devices.
Mask out unsupported algorithms and services based on the value read in
the fuse register.
This includes only capabilities for the crypto service.
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
Reviewed-by: Marco Chiappero <marco.chiappero@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to '')
| -rw-r--r-- | drivers/crypto/qat/qat_common/icp_qat_hw.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/crypto/qat/qat_common/icp_qat_hw.h b/drivers/crypto/qat/qat_common/icp_qat_hw.h index e39e8a2d51a7..5770b2b2c09e 100644 --- a/drivers/crypto/qat/qat_common/icp_qat_hw.h +++ b/drivers/crypto/qat/qat_common/icp_qat_hw.h @@ -91,7 +91,14 @@ enum icp_qat_capabilities_mask { ICP_ACCEL_CAPABILITIES_RAND = BIT(7), ICP_ACCEL_CAPABILITIES_ZUC = BIT(8), ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9), - /* Bits 10-25 are currently reserved */ + /* Bits 10-11 are currently reserved */ + ICP_ACCEL_CAPABILITIES_HKDF = BIT(12), + ICP_ACCEL_CAPABILITIES_ECEDMONT = BIT(13), + /* Bit 14 is currently reserved */ + ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15), + ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16), + ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17), + /* Bits 18-25 are currently reserved */ ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26) }; |