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| author |   Shirish S <shirish.s@amd.com> | 2020-01-27 16:35:24 +0530 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-02-25 11:30:42 -0500 |
| commit | a3ed353cf8015ba84a0407a5dc3ffee038166ab0 (patch) | |
| tree | 30b146d5cd704e2d21bb4fd606eb29cb4a1ae2bb /drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h | |
| parent | drm/amdgpu: fix memory leak during TDR test(v2) (diff) | |
| download | linux-dev-a3ed353cf8015ba84a0407a5dc3ffee038166ab0.tar.xz linux-dev-a3ed353cf8015ba84a0407a5dc3ffee038166ab0.zip | |
amdgpu/gmc_v9: save/restore sdpif regs during S3
fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM.
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h index b6f74bf4af02..27bb8c1ab858 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h @@ -7376,6 +7376,8 @@ #define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e #define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x395d +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 // addressBlock: dce_dc_fmt4_dispdec // base address: 0x2000 |