diff options
author | Prike Liang <Prike.Liang@amd.com> | 2020-03-02 09:36:15 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2020-03-05 09:42:08 -0500 |
commit | 80381d40c9bf5218db06a7d7246c5478c95987ee (patch) | |
tree | f3f6ea8f9e2b320e5a17fd67e0e00783d21a9214 /drivers/gpu/drm/amd/powerplay/smu_v12_0.c | |
parent | drm/amd/display: fix dcc swath size calculations on dcn1 (diff) | |
download | linux-dev-80381d40c9bf5218db06a7d7246c5478c95987ee.tar.xz linux-dev-80381d40c9bf5218db06a7d7246c5478c95987ee.zip |
drm/amd/powerplay: fix pre-check condition for setting clock range
This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse
dpm clock layout and a zero frequency dpm level as following case.
cat pp_dpm_mclk
0: 1200Mhz
1: 1200Mhz
2: 800Mhz
3: 0Mhz
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to '')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c index 870e6db2907e..518e6597bf2d 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c @@ -458,9 +458,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ { int ret = 0; - if (max < min) - return -EINVAL; - switch (clk_type) { case SMU_GFXCLK: case SMU_SCLK: |