diff options
author | Jani Nikula <jani.nikula@intel.com> | 2021-09-09 15:52:04 +0300 |
---|---|---|
committer | Jani Nikula <jani.nikula@intel.com> | 2021-09-20 18:47:00 +0300 |
commit | e01163e82b708535ae1bfca67730516578b237be (patch) | |
tree | 9ee70c7e8cce7eba953be67ae0d582577b8467d6 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
parent | drm/i915/dg2: use 128b/132b transcoder DDI mode (diff) | |
download | linux-dev-e01163e82b708535ae1bfca67730516578b237be.tar.xz linux-dev-e01163e82b708535ae1bfca67730516578b237be.zip |
drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b
There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.
v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper
Bspec: 54128
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a2902cc188973f022f282f2a77e693afdecefb5a.1631191763.git.jani.nikula@intel.com
Diffstat (limited to '')
-rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index f7a0470b1f1c..fd0a31bc3dcd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, clear_act_sent(encoder, pipe_config); + if (intel_dp_is_uhbr(pipe_config)) { + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); + + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); + } + intel_ddi_enable_transcoder_func(encoder, pipe_config); intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, |