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authorVille Syrjälä <ville.syrjala@linux.intel.com>2021-09-21 18:25:17 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2021-09-24 15:55:02 +0300
commit09bbdd8730dce85db1d945961dbf0ea4066eb6d6 (patch)
treea6b510548dea3175dc3105e156bfcd81707cf4ee /drivers/gpu/drm/i915/display/intel_fbc.c
parentdrm/i915/fbc: Implement Wa_16011863758 for icl+ (diff)
downloadlinux-dev-09bbdd8730dce85db1d945961dbf0ea4066eb6d6.tar.xz
linux-dev-09bbdd8730dce85db1d945961dbf0ea4066eb6d6.zip
drm/i915/fbc: Allow higher compression limits on FBC1
On FBC1 we can specify an arbitrary cfb stride. The hw will simply throw away any compressed line that would exceed the specified limit and keep using the uncompressed data instead. Thus we can allow arbitrary compression limits. The one thing we have to keep in mind though is that the cfb stride is specified in units of 32B (gen2) or 64B (gen3+). Fortunately X-tile is already 128B (gen2) or 512B (gen3+) wide so as long as we limit outselves to the same 4x compression limit that FBC2 has we are guaranteed to have a sufficiently aligned cfb stride. Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210921152517.803-5-ville.syrjala@linux.intel.com
Diffstat (limited to '')
-rw-r--r--drivers/gpu/drm/i915/display/intel_fbc.c20
1 files changed, 7 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 37ebed8d228d..46f62fdf9eee 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -164,15 +164,13 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc *fbc = &dev_priv->fbc;
+ const struct intel_fbc_reg_params *params = &fbc->params;
int cfb_pitch;
int i;
u32 fbc_ctl;
- /* Note: fbc.limit == 1 for i8xx */
- cfb_pitch = params->cfb_size / FBC_LL_SIZE;
- if (params->fb.stride < cfb_pitch)
- cfb_pitch = params->fb.stride;
+ cfb_pitch = params->cfb_stride / fbc->limit;
/* FBC_CTL wants 32B or 64B units */
if (DISPLAY_VER(dev_priv) == 2)
@@ -518,18 +516,14 @@ static int intel_fbc_min_limit(int fb_cpp)
static int intel_fbc_max_limit(struct drm_i915_private *dev_priv)
{
- /*
- * FIXME: FBC1 can have arbitrary cfb stride,
- * so we could support different compression ratios.
- */
- if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
- return 1;
-
/* WaFbcOnly1to1Ratio:ctg */
if (IS_G4X(dev_priv))
return 1;
- /* FBC2 can only do 1:1, 1:2, 1:4 */
+ /*
+ * FBC2 can only do 1:1, 1:2, 1:4, we limit
+ * FBC1 to the same out of convenience.
+ */
return 4;
}