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| author |   José Roberto de Souza <jose.souza@intel.com> | 2019-08-20 15:33:24 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-08-22 13:09:16 -0700 |
| commit | 99fc38b12095cd0ca9fc5b8c8e27e827dff6ed34 (patch) | |
| tree | 960f55d487b89c43693e672cf061498adadedda3 /drivers/gpu/drm/i915/display/intel_psr.c | |
| parent | drm/i915/psr: Make PSR registers relative to transcoders (diff) | |
| download | linux-dev-99fc38b12095cd0ca9fc5b8c8e27e827dff6ed34.tar.xz linux-dev-99fc38b12095cd0ca9fc5b8c8e27e827dff6ed34.zip | |
drm/i915: Add transcoder restriction to PSR2
According to PSR2_CTL definition in BSpec there is only one instance
of PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2
on TRANSCODER_EDP while on TGL PSR2 is only supported by
TRANSCODER_A.
Since BDW PSR is allowed on any port, but we need to restrict by
transcoder.
v8: Renamed _psr2_supported_in_trans() to psr2_supported() (Lucas)
v9: Renamed psr2_supported() to transcoder_has_psr2() (Ville)
BSpec: 7713
BSpec: 20584
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190820223325.27490-2-jose.souza@intel.com
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 77232f6bca17..771d9a40bf12 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -534,6 +534,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); } +static bool +transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) +{ + if (INTEL_GEN(dev_priv) >= 12) + return trans == TRANSCODER_A; + else + return trans == TRANSCODER_EDP; +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -545,6 +554,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (!dev_priv->psr.sink_psr2_support) return false; + if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { + DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n", + transcoder_name(crtc_state->cpu_transcoder)); + return false; + } + /* * DSC and PSR2 cannot be enabled simultaneously. If a requested * resolution requires DSC to be enabled, priority is given to DSC |